Testing semiconductor integrated circuits is well known, including the use of test modes for module level testing of dynamic random access memories providing memory chips and circuits with a plurality of test mode options to insure product reliability.
In U.S. Pat. No. 4,468,759, granted to R. I. Kung et al, there is disclosed a testing system or method for dynamic random access memories wherein a higher stored reference voltage in the dummy cells is used when reading binary ones from the memory and a lower dummy reference is used when reading binary zeroes to predict the memory's performance under stressful environmental conditions before packaging the memory chip.
U.S. Pat. No. 4,751,679, granted to S. Dehganpour, discloses a test mode in a dynamic random access memory wherein gates of all transfer devices of the memory cell are subjected to a voltage stress test to provide an accelerated test of the integrity of the gate insulator.
In an article entitled "CMOS Memory Sorted for Yield Versus Reliability" by K. S. Gray et al, in Research Disclosure, May 1987, Number 277, page 27718, published by Kenneth Mason Publications Ltd, England, there is disclosed a system for sorting semiconductor memory chips for high reliability applications by testing for an acceptable output signal from chips without the use of bootstrapped word lines and for high yield of chips for use in applications not requiring the higher reliability with the use of bootstrapped word lines. Word line bootstrapping is enabled on chips by blowing a fuse or changing a D.C. voltage level on a pad.